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1 single output lnb supply and control voltage regulator with i 2 c interface for satellite set-top box designs isl9492 the isl9492 is a highly integrated voltage regulator and interface ic specifically designed for supplying power and control signals from adva nced satellite set-top box (stb) modules to the low noise blocks (lnb) of a single antenna port. it also supports diseqc tone generation and modu lation with diagnostic status read-back. controlling the isl9492 is simple via the i 2 c bus by writing 8 bit words onto the system registers (sr). the device design makes the to tal lnb supply design simple, efficient and compact with low external component count by integrating boost power mosfet, current-mode boost pwm and a low-noise linear regulator. the current-mode boost converters provide the linear regulator with input voltage that is set to the final output voltages, plus typically 0.9v to insure minimum power dissipation across each linear regulator. the lnb output voltage can be controlled in two ways; by full control from i 2 c using the vtop and vbot bits or by setting the i 2 c to the lower range and switching to higher range with the select vtop pin. the external modulation input ex tm accepts a modulated diseqc command and transfers it symmetrically to the output. the extm pin can be used to modulate the continuous internal tone. the fault signal serves as an interrupt fo r the processor when any condition turns off the lnb controller (o ver-temperature, overcurrent, disable). the states of these flags to the faults can be thoroughly examined through the i 2 c registers. features ? single-chip power solution - operation for 1-tuner/1-dish applications - integrated dc/dc converter and i 2 c interface ? integrated boost mosfet ? switch-mode power converter for lowest dissipation - 490khz boost switching frequency - boost pwms with > 92% efficiency - selectable 13.5v or 18.5v outputs -i 2 c and pin controllable output ? 31v output back-bias capability ? built-in tone oscillator factory - facilitates diseqc (eutelsat) encoding -trimmed to 22khz - external modulation input ? diseqc 2.0 support and diagnostics ? internal overvoltage, undervoltage, overcurrent protection, over-temperature flags accessible through the i 2 c interface and fault signal status pin ? short-circuit protection applications ? lnb power supply and control for satellite set-top box figure 1. typical application r1 100k c4 1f c8 0.22f c9 0.22f c6 0.1f c10 100f c11 10f nds356ap l1 10h l3 220h r2 15 flt# scl sda cpvout 27 cpswout 28 cpswin 1 vcc 6 ldo_sgnd 20 ldo_sgnd 25 abyp 5 pgnd 9 pgnd 8 drain 7 vswsns 2 vsw 26 vout 24 nc 3 dgate 23 nc 4 tcap 22 dbyp 10 sda 16 scl 17 flt# 21 extm 19 tdout 15 tdin 14 txt 18 svtop 13 addr1 12 addr0 11 isl9492 d1 cms06 l2 1h c7 100f c5 2.2nf c1 0.047f c2 1f c3 1f extm tdout txt lnb power vin c10 0.1f 3.3v q1 d4 cms06 d2 tvs rp 100 ferrite bead d3 cms06 100 rl cp see pg 14 march 17, 2011 fn6547.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl9492 2 fn6547.1 march 17, 2011 pin configuration isl9492 (28 ld tqfn) top view ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # isl9492erz 94 92erz -20 to +85 28 ld 4x4 tqfn l28.4x4a ISL9492QFNEVAL1 evaluation board 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ specia l pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs comp liant and compatible with both snpb and pb-free soldering opera tions). intersil pb- free products are msl classified at pb-free peak reflow temperat ures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl9492 . for more information on msl please see techbrief tb363. 1 2 3 4 5 6 7 8 910111213 20 19 18 17 16 15 21 cpswin vswsns nc nc abyp vcc drain dbyp pgnd addr0 svtop cpswout cpvout vsw ldo_sgnd vout dgate flt ldo_sgnd extm txt scl sda tdout 28 27 26 25 24 23 tdin tcap 14 22 addr1 pgnd functional pin descriptions pin symbol function 1 cpswin charge pump connection 1 2 vswsns boost regulator sense line. connect to boost output capacitor. 3, 4 nc no connect pins 5 abyp analog 5v supply. decouple with 1f ceramic capacitor and a ferrite bead (see ?abyp? on page 14 for more detail). 6 vcc main power supply to the chip. 7 drain this is the drain of the boost mosfet. th e boost inductor will be connected to this pin. 8,9 pgnd power gound for the internal boost mosfet. 10 dbyp digital 5v supply. decoup le with 1f ceramic capacitor. 11, 12 addr0, addr1 logic combination at the add0 and a dd1 can select four different chip select addresses. 13 svtop external control of output voltage selection. 14 tdin tone detector input. 15 tdout the envelope of the actually detected exte rnal tone signal. it is an open-drain output.
isl9492 3 fn6547.1 march 17, 2011 16 sda bidirectional data from/to i 2 c bus. 17 scl clock from i 2 c bus. 18 txt tx, rx switch control 19 extm this pin can be used in two ways: 1. to drive tone with the ac tual tone signal directly. 2. to drive tone with the envelope of the actual tone signal to be generate by this device. 20, 25 ldo_sgnd small signal gr ound for the internal ldo. 21 flt this is an open drain output from the controller. it will go low when any of the fault flags is set. 22 tcap capacitor for setting rise and fall time of the output voltage. typical value is 0.1f. 23 dgate connect to an external pmos gate to short the rlc tank circuit during 22khz tone transmission. 24 vout linear regulator output provides the lnb power. 26 vsw input to the linear regulator that actually provides the lnb output voltage. 27 cpvout output of charge pump. 28 cpswout charge pump connection 2. - pad there is no connection with this pin. epad also has no connection and should be connected to gnd plane with multiple vias. functional pin descriptions (continued) pin symbol function
isl9492 4 fn6547.1 march 17, 2011 block diagram counter overcurrent protection logic scheme 1 olf/bcf dcl oc1 pwm logic q s drain slope compensation 19 11 17 22 24 27 6 vout vcc ldo_sgnd ent cpvout charge pump thermal shutdown otf olf/bcf sda isell&h en vtop vbot dcl scl ent osc1 interface band gap ref voltage adj1 ref voltage en soft-start int 5v on chip linear uvlo por soft-start 20, 25 26 vsw vbg2 5 vbg1 tone ckt msel 14 15 tdin tdout tone decoder 16 28 1 13 txt 12 21 tth tth 18 txt divide pgnd 7 svtop 10 dbyp 4 3 nc nc 2 vswsns abyp 23 dgate tth txt osc2 8,9 + - + - + - scl sda i 2 c extm cpswout cpswin tcap ouvf flt addr0 addr1
isl9492 5 fn6547.1 march 17, 2011 typical application schematic r1 100k c4 1f c8 0.22f c9 0.22f c6 0.1f c10 100f c11 10f nds356ap l1 10h l3 220h r2 15 flt# scl sda cpvout 27 cpswout 28 cpswin 1 vcc 6 ldo_sgnd 20 ldo_sgnd 25 abyp 5 pgnd 9 pgnd 8 drain 7 vswsns 2 vsw 26 vout 24 nc 3 dgate 23 nc 4 tcap 22 dbyp 10 sda 16 scl 17 flt# 21 extm 19 tdout 15 tdin 14 txt 18 svtop 13 addr1 12 addr0 11 isl9492 d1 cms06 l2 1h c7 100f c5 2.2nf c1 0.047f c2 1f c3 1f extm tdout txt lnb power vin c10 0.1f 3.3v q1 d4 cms06 d2 tvs rp 100 ferrite bead d3 cms06 100 rl cp see pg 14
isl9492 6 fn6547.1 march 17, 2011 table of contents functional pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 tone waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 typical performance curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 derated performance curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 diseqc encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 diseqc decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 abyp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 device enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 diseqc external mosfet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 boost regulator inductor and output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 thermal protection and fault indicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 i2c bus interface for isl9492 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 isl9492 software description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 system register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 transmitted data (i 2 c bus write mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 received data (i2c bus read mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 power?on i2c interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 add0 and add1 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
isl9492 7 fn6547.1 march 17, 2011 absolute maximum rating s thermal information v cc (supply voltage). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8v to 18v v out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 36v vsw, drain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 24v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 5.5v all pins referenced to ground esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 3kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 200v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv latch up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance ja (c/w) jc (c/w) tqfn package (notes 4, 5) . . . . . . . . . . . . . 38 3 maximum junction temperature (note 6). . . . . . . . . . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-40c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions ambient temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the "case temp" location is the center of the exposed metal pad on the package underside. 6. the device junction temperature should be kept below +150c. th ermal shutdown circuitry turns off the device if junction temp erature exceeds +150c typically. electrical specifications v cc = 12v, t a = -20c to +85c, unless otherwise noted. typical values are at t a = +25c. en = 1, vtop = 0, vbot = 0, ent = 0, v out load = 100ma, unless otherwise noted. see ?isl9492 software description? on page 16 for i 2 c access to the system. boldface limits apply over the operating temperature range, -20c to +85c. parameter symbol test conditions (note 7) min (note 8) typ max (note 8) units operating supply voltage range f 8 12 14 v standby supply current en = 0 f - 3.6 - ma supply current i in vtop = vbot = en = 1, dlin = 0, v out =no load f - 6 10 ma supply current i vsw vtop = vbot = en = dlin = 1, no load f - - 20 ma temperature shutdown threshold f - 150 - c temperature shutdown hysteresis f - 20 - c undervoltage lockout boost falling threshold ouvl v cc falling from above 8v (note 9) f - 6.8 - v rising threshold ouvl v cc rising from 0v f - 7.35 - v boost converter boost mosfet drain current limit f-4-a boost mosfet on-resistance f - 520 - m linear regulator output voltage 13v (see table 1) p 13.2 13.5 13.8 v 14v (see table 1) p 13.9 14.2 14.5 v 18v (see table 1) p 18.2 18.5 18.8 v 20v (see table 1) p 19.7 20 20.3 v dropout voltage v drop v out load = 750ma (note 9) f - 0.4 - v t cap current (output soft-start control) t cap = 0v f 8 10 12 a output undervoltage (asserted high during soft-start) ouvf bit is asserted hi gh, measured from the typical output set value p -12 - -2 % output overvoltage (asserted high during soft-start) ouvf bit is asserted hi gh, measured from the typical output set value p +2 - +12 %
isl9492 8 fn6547.1 march 17, 2011 line regulation v cc = 8v to 14v; v out = 13v @ 350ma p - 4 40 mv v cc = 8v to 14v; v out = 18v @ 350ma p - 4 60 mv load regulation v out load = 0ma to 350ma p - 50 80 mv v out load = 0ma to 750ma p - 100 200 mv current limiting i max iselh = 0, isell = 0, dcl bit = 0 (note 10) p 850 950 1050 ma iselh = 1, isell = 0, dcl bit = 0 (note 10) p 600 670 740 ma iselh = 0, isell = 1, dcl bit = 0 (note 10) p 710 790 870 ma iselh = 1, isell = 1, dcl bit = 0 (note 10) p 370 400 450 ma cable fault cabf threshold i cab v out = 20v, no tone p 2 20 50 ma back-biased current v out = 21v from external source p - - 10 ma tone oscillator (tone) (note 8) tone frequency f tone ent = 1 p 20 22 24 khz tone amplitude v tone ent = 1, with proper diseqc tank circuit p 500 680 800 mv tone duty cycle dc tone ent = 1 p - 50 - % tone rise or fall time t r , t f ent = 1 p 5 10 14 s tone decoder (tdin, tdout) frequency capture range ftdin p 18 - 26 khz input impedance zdet f - 8.6 - k detector output voltage v tdout_l tone present, sink current = 3ma p - - 0.4 v detector output leakage (open drain) i tdout_h tone absent p - - 10 a tone decoder rx threshold (note 10) v rxth tth bit = 0 and txt pin = 0 p 200 --mv p-p tone decoder tx threshold (note 10) v txth tth bit= 1 or txt pin = 1 p 400 --mv p-p logic interface (input = extm, svtop, add0, add1, txt, scl, sda, output = flt ) input logic low f-- 0.8 v input logic high f 2.0 -- v input current f - 25 - a input pull-down resistance f - 200 - k output logic low fault detected, sink current = 3ma f - - 0.4 v output logic high leakage (open drain) no fault f - - 10 a notes: 7. f = functional check; p = probe or final test 8. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. 9. output voltage can only be maintained in regulation if the input voltage is within the specified range. electrical specifications v cc = 12v, t a = -20c to +85c, unless otherwise noted. typical values are at t a = +25c. en = 1, vtop = 0, vbot = 0, ent = 0, v out load = 100ma, unless otherwise noted. see ?isl9492 software description? on page 16 for i 2 c access to the system. boldface limits apply over the operating temperature range, -20c to +85c. (continued) parameter symbol test conditions (note 7) min (note 8) typ max (note 8) units
isl9492 9 fn6547.1 march 17, 2011 tone waveform notes: 10. tth allows threshold control through the i 2 c interface. 11. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 12. the tone rise and fall times are not shown due to resolution of graphics. figure 2. tone waveform ent msel extm vout 22khz 22khz 22khz 22khz 22khz 22khz i 2 c i 2 c pin pin returns to nominal v out ~1 period external tone internal tone (note 12)
isl9492 10 fn6547.1 march 17, 2011 typical performance curves figure 3. boost efficiency for 12v in to 14.3v out figure 4. system efficiency (boost + ldo) for 12v in to 13.3v out figure 5. vlnb rise time = 29ms, t cap = 0.22f figure 6. boost switch node at 0a (discontinuous) figure 7. boost switch node at 100ma (partial discontinuous) figure 8. boost switch node at 300ma (continuous mode) 60 70 80 90 100 0 i load 0.10.20.30.40.50.60.70.80.9 efficiency (%) 60 65 70 75 80 85 90 95 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 i load efficiency (%)
isl9492 11 fn6547.1 march 17, 2011 figure 9. vlnb transitions from 13.3v to 18.3v f igure 10. vlnb transitions from 18.3v to 13.3v figure 11. 22khz tone at no-load figure 12. 22khz tone at 700ma figure 13. ac noise on 13.3v out at 700ma is ~ 10mv figure 14. dynamic current loop started to enable. top is vlnb and bottom is load current waveform (200ma/div) typical performance curves (continued)
isl9492 12 fn6547.1 march 17, 2011 figure 15. isl9492 shorted to gnd in dynamic mode. top is vlnb and bottom is load current waveform (200ma/div) figure 16. isl9492 shorted to gnd in static mode causes thermal shutdown. top is vlnb and bottom is load current waveform (200ma/div) figure 17. isl9492 extm signal going low to high and high to low vs tone enabled on output delay figure 18. extm going high to tone enabled on the output delay is ~500ns figure 19. extm going low to tone disabled on the output delay is ~750ns figure 20. isl9492 ent bit going high to tone enabled on the output delay typical performance curves (continued) 22khz tone extm pulse 22khz tone extm pulse 22khz tone extm pulse
isl9492 13 fn6547.1 march 17, 2011 \ figure 21. ent bit going high to tone enabled on the output delay is ~34s figure 22. isl9492 ent bit going low to tone disabled on the output delay figure 23. ent bit going low to tone disabled on the output delay is ~32s typical performance curves (continued) derated performance curve figure 24. output current derating 0 100 200 300 400 500 600 700 800 020406080 temperature (c) load (ma)
isl9492 14 fn6547.1 march 17, 2011 functional description the isl9492 single output voltage regulator is an ideal choice for advanced satellite set-top box and personal video recorder applications. the device utilizes built-in dc/dc step-up converters that generate a voltage for the linear regulator with minimal power dissipation. an undervoltage lockout circuit disables the device when v cc drops below a fixed threshold. diseqc encoding the tone signal can be generated in many different ways. external tone on the extm pin ca n be used when the ent bit is low and the msel bit is high. th e isl9492 will inject an internal tone on v out as long as: ? the extm pin is low, the ent bit is high and the msel bit is low ? the ent and msel bits are low and the extm pin is high diseqc decoder if a tone signal is detected within the specified frequency range on tdin thru a 10nf from v out , the open drain pin tdout is asserted low. the detector threshold is 200mv (tth bit = 0 and txt pin is 0) in the receive mode and 400 mv (tth = 1 or txt = 1) in the transmit mode. abyp the abyp pin provides 5v bias to the internal analog circuitry and the digital i 2 c block and is susceptible to noise pickup due to integrated high power boost mosfet. in order to minimize any disturbance preventing the normal operation of the chip, it is recommended to add a ferrite bead (tdk part # mmz1608s102a) in series with the decoupling capacitor. device enable the device can be enabled or di sabled through the en and dlin bits. when both the en and dlin bits are low (default state), both the boost converter and the linear regulator are shut down, in which case, the boost output voltage will be vin - vdiode and the linear regulator will be at 0v . when both the en and dlin bits are high, both power blocks are enabled. when the en bit is high and the dlin bit is low, the boost circuit is enabled and the linear regulator will be disabled. diseqc external mosfet to transmit diseqc tone to the outside world, the external mosfet q1 in the ?typical application schematic? on page 5 has to be turned on by pulling the txt pin or the tth bit high. in order to receive tone from the lnb, the txt pin or tth bit should be pulled low. linear regulator in order to minimize the power di ssipation, the output voltage of the boost converter is regulated to a voltage slightly higher than the desired lnb output voltage. the linear regulator has the capability to sink and source current from the lnb where this highly desirable feature allows full modulation capability into capacitive loads as high as 0.75f. boost regulator inductor and output capacitor selection the isl9492 boost regulator is internally compensated and relies on the inductor and output capacitor value for overall loop stability. it is recommended that the boost inductor be in the 8h to 15h range and the output capacitor in the 50f to 200f range with a worst case esr of 40m ? to 125m ? . in case if the output capacitor is an aluminum electrolytic type, special attention should be paid to the increased esr at low temperature due to freezing liquid electrolyte at around 0c. the increased esr can interfere with the overall stability by introducing a zero much sooner than anticipated at 1/2 * r_esr* c out . the following are some recommended part numbers which meet the ab ove mentioned criteria: ? l = 10h inductor - sumida # cdr7d43mn-100 ?c out = 180f capacitor - panasonic # ekze500ell181mh20d in case the output capacitor esr is outside the recommended range, an additional external pole comprised of rp and cp needs to be inserted on vswsns as shown in figure 25 so that it cancels the esr zero. assuming c out _esr = 230m , c out = 100f and rp = 100 ? , then cp is calculated to be 0.22f, as shown in equation 1. the voltage rating on th is capacitor should be in the 25v to 35v range since it is connected to the boost v out rail. output timing the output voltage rise and fall times can be set by an the external capacitor on the tcap pin. the output rise and fall times is given by equation 2: where c is the tcap value in nf, t is the required transition time in ms and v is the differential transiti on voltage from low output voltage range to the high output range in volts. too large a value of tcap prevents the output from rising to the nominal value, within the soft-start time when the error amplifier is released. too small a value of the tcap can cause high peak currents in the boost circuit. for example, a 10v/ms slew on a 80f vsw cp esr cout 100 ------------------------------ = (eq. 1) figure 25. additional pole adde d by rp and cpd cnd cp to compensate high esr zero l1 10h pgnd 8 drain 7 vswsns 2 d1 cms06 c7 100f rp 100 cp 0.22f c 10t v --------- - = (eq. 2)
isl9492 15 fn6547.1 march 17, 2011 capacitor with an inductor of 15h can cause a peak inductor current of approximately 1a. output voltage selection the device offers a flexible means to select the output voltage. when vspen is low, the output voltage can be selected by the svtop pin. in this case, when the svtop pin is low, the output voltage is either 13v or 14v, depending on the vbot bit. when the svtop pin is high, the output voltage is either 18v or 20v depending on the vtop bit. when vspen is high, the svtop pin is ignored, and the output is selected by both the vtop and the vbot bits. see table 1. current limiting both the boost converter and the linear regulator have independent current limit. in the bo ost converter, this is achieved through cycle-by-cycle internal current limit. in the linear regulator, current limit threshol d is set by the iselh and isell bits (see table 9). at any time, when the linear regulator goes into current limit and the dcl bit is high, the olf bit is set. olf bit is not affected by current limit occurred through the boost converter. in this mode, the part will deliver the full specified current for 50ms. during this time , if the current limit condition disappears, the olf bit will be cleared and the part restarts. if the part is still in current limit after this time period, the linear regulator and boost converter will automatically disable for 900ms to prevent the part from overheating. after this shutdown period, the isl9492 will automatica lly re-enable itself and the above described sequence will repeat. this current limit method is also called ?dynamic current limit?. the isl9492 can also be configured so when a current limit is detected, the part rather than disabling the linear regulator after 50ms stays powered up and delivers the programmed load current in a constant current mode. this mode can be enabled by writing a ?0? in the dcl bit. in this mode, the olf bit is set high to indicate an overcurrent condition. this current limiting method is also called ?static current limit?. this method can be used to enable any loads which are highly capacitive during start-up. thermal protection and fault indicator when the junction temperature reaches the critical temperature, the boost converter and the linear regulator are immediately disabled with the otf bit set. on ly when the junction temperature cools down to a lower temperature threshold specified will this bit will be cleared and the part be allowed to restart. when any of the fault handling flags (otf, cabf, ouvf, olf, bcf) are set, the fault indicator pin flt will go low. this status output can serve as an interrupt signal to a microcontroller. the ouvf bit will be low indicating the output voltage is good and within 90% of final steady-state dc value, so during output voltage transitions, this bit will go high indicating output voltage is out of regulation followed by going low; see figure 4. this bit can be used as an output for the system to know that the lnb output voltage is in regulation and it can start communicating with the lnb by transmitting the 22khz tone . the system will be able to apply internal or external tone on ly after the ouvf bit is pulled low and during tone application, the bit will stay latched low. bcf bit is set when back bias is detected; olf bit is set when an overcurrent is detected; cabf bit is set low when there is maximum of 50ma of load current; otf bit is set when the die junction temperature reaches +150c; all these registers are activated after the ldo is enabled by the dlin bit in sr4 register. i 2 c bus interface for isl9492 (refer to philips i 2 c specification, rev. 2.1) data transmission from main mi croprocessor to the isl9492 and vice versa takes place through the two-wire i 2 c bus interface, consisting of the two lines sda and scl. both sda and scl are bidirectional lines, connected to a positive supply voltage via a pull- up resistor. (pull-up resistors to positive supply voltage must be externally connected). when the bus is free, both lines are high. the output stages of isl9492 will have an open drain/open collector in order to perform the wired-and function. data on the i 2 c bus can be transferred up to 100kbps in the standard-mode or up to 400kbps in the fast-mode. the level of logic ?0? and logic ?1? is defined in the ?electrical specifications? table on page 8. one clock pulse is generated for each data bit transferred. data validity the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low. refer to figure 27. table 1. vspen vtop vbot svtop vout 0x0013.5v 0x1014.2v 00x118.5v 0 1 x 1 20v 1 0 0 x 13.5v 101x14.2v 1 1 0 x 18.5v 111x20v figure 26. output power sequence 12% 12% dlin bit vspen/svtop ouvf bit vlnb 22khz tone 22khz tone sda scl data line stable data valid change of data allowed figure 27. data validity
isl9492 16 fn6547.1 march 17, 2011 start and stop conditions as shown in figure 28, start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition on the sda line while scl is high. a stop condition must be sent before each start condition. byte format every byte put on the sda line must be 8 bits long. the number of bytes that can be transmitted per transfer is unrestricted. each byte has to be followed by an acknowledge bit. data is transferred with the most significant bit first (msb). acknowledge the master (microprocessor) puts a resistive high level on the sda line during the acknowledge clock pulse (figure 29). the peripheral that acknowledges has to pull-down (low) the sda line during the acknowledge clock pulse, so that the sda line is stable low during this clock pulse. (note that set-up and hold times must also be taken into account.) the peripheral which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the sda line remains at the high level du ring the ninth clock pulse time. in this case, the master transmitter can generate the stop information in order to abort the transfer. the isl9492 will not generate the acknowledge if the power ok signal from the uvlo is low. transmission without acknowledge avoiding detection of the ackn owledgement, the microprocessor can use a simpler transmission; it waits one clock without checking the slave acknowledging, and sends the new data. this approach, however, is less protected from error and decreases the noise immunity. isl9492 software description interface protocol the interface protocol is comprised of the following, as shown in table 2: ? a start condition (s) ? a chip address byte (msb on left; the lsb bit determines read (1) or write (0) transmission) (the assigned i 2 c slave address for the isl9492 is 0001 0xx) ? a sequence of data (1 byte + acknowledge) ? a stop condition (p) system register format ? r, w = read and write bit ? r = read-only bit all bits reset to 0 at power-on table 6. control register (sr4) transmitted data (i 2 c bus write mode) when the r/w bit in the chip is set to 0, the main microprocessor can write on the system registers (sr2 thru sr4) of the isl9492 via i 2 c bus. these will be written by the microprocessor as shown in table 7. the spare bits of registers are reserved for further use. sda scl start condition figure 28. start and stop waveforms stop condition sp sda scl figure 29. acknowledge on the i 2 c bus 1 2 8 9 acknowledge from slave msb start table 2. interface protocol s 0 0 0 1 0 a1 a0 r/w ack data (8 bits) ack p table 3. status register (sr1) r, wr, wr, w r r r r r sr1h sr1m sr1l otf cabf ouvf olf bcf table 4. tone register (sr2) r, w r, w r, w r, w r, w r, w r, w r, w sr2h sr2m sr2l ent msel tth res* res* table 5. command register (sr3) r, w r, w r, w r,w r, w r,w r, w r, w sr3h sr3m sr3l res* vspen dcl iselh isell r, w r, w r, w r, w r, w r, w r, w r, w sr4h sr4m sr4l en dlin res* vtop vbot
isl9492 17 fn6547.1 march 17, 2011 table 7. status register sr1 configuration sr1h sr1m sr1l otf cabf ouvf olf bcf function 000xxxxxsr1 selected 0 0 0 x x x 0 x no current limit detected 0 0 0 x x x 1 x current limit detected in the linear regulator 0 0 0 x x x x 0 no back-bias detected 0 0 0 x x x x 1 back-bias detected 000xx0xxv out within specified range 000xx1xxv out not within specified range 000x0xxxcable connected 000x1xxxcable open 0 0 0 0 x x x x junction normal temperature 0 0 0 1 x x x x junction over-temperature reached table 8. tone register sr2 configuration sr2h sr2m sr2l ent msel tth res* res* function 001xxx00sr2 selected 0 0 1 0 0 x 0 0 tone generated internally according to the state of the extmpin 0 0 1 0 1 x 0 0 tone supplied by extm pin 0 0 1 1 0 x 0 0 tone generated internally regardless of the extm pin 001xx000decoder rx threshold set 001xx100decoder tx threshold set note: x indicates ?read only? and is a ?don?t care? for the write mode. res* is a reserved bit and should be ?0? table 9. command register sr3 configuration sr3h sr3m sr3l res* vspen dcl iselh isell function 0100xxxxsr3 selected 0100x1xxdynamic current limit 0100x0xxstatic current limit 0 1 0 0 x x 1 1 vout current limit set to 400ma 0 1 0 0 x x 1 0 vout current limit set to 670ma 0 1 0 0 x x 0 1 vout current limit set to 790ma 0 1 0 0 x x 0 0 vout current limit set to 950ma 01000xxxsvtop pin enabled 0 1 0 0 1 x x x svtop pin disabled note: x indicates ?read only? and is a ?don?t care? for the write mode. res* is a reserved bit and should be ?0?
isl9492 18 fn6547.1 march 17, 2011 received data ( i 2 c bus read mode) the isl9492 can provide to the master a copy of the system register information via the i 2 c bus in read mode. the read mode is master activated by sending th e chip address with r/w bit set to 1. at the following master generated clock bits, the isl9492 issues a byte on the sda data bus line (msb transmitted first). at the ninth clock bit the mcu master can: ? acknowledge the reception, starting in this way the transmission of another byte from the isl9492. ? not acknowledge, stopping the read mode communication. the read only bits of the re gister sr1 convey diagnostic information about the isl9492, as indicated in table 7. power?on i 2 c interface reset the i 2 c interface built into the isl9492 is automatically reset at power-on. the i 2 c interface block will receive a power ok logic signal from the uvlo circuit. this signal will go high when chip power is ok. as long as this signal is low, the interface will not respond to any i 2 c commands and the system register sr1 thru sr4 are all initialized to all zero, thus keeping the power blocks disabled. once the v cc rises above uvlo, the power ok signal to the i 2 c is asserted high, and the i 2 c interface becomes operative and the sr?s can be configured by the main microprocessor. about 400mv of hysteresis is provided in the uvlo threshold to avoid false triggering of the power-on reset circuit. (i 2 c comes up with en = 0; en goes high at the same time as (or later than) all other i 2 c data for that pwm becomes valid). add0 and add1 pins connecting these pins to gnd, the chip i 2 c interface address is 0001000, but, it is possible to choose between four different addresses by setting these pins to the logic levels indicated in table 11. table 10. control register sr4 configuration sr4h sr4m sr4l en dlin res* vtop vbot function 011xx0xxsr4 selected 0 1 1 0 x 0 x x device disabled 0111x0x0v out = 13.4v if vspen = 0 and svtop = 0 0111x0x1v out = 14.4v if vspen = 0 and svtop = 0 0111x00xv out = 18.7v if vspen = 0 and svtop = 1 0111x01xv out = 20v if vspen = 0 and svtop = 1 0111x000v out = 13.4v if vspen = 1 and svtop = x 0111x001v out = 14.4v if vspen = 1 and svtop = x 0111x010v out = 18.7v if vspen = 1 and svtop = x 0111x011v out = 20v if vspen = 1 and svtop = x 0 1 1 1 0 0 x x internal linear regulator is turned-off but boost circuit is on 0 1 1 1 1 0 x x internal linear regulator is turned-on and boost circuit is on note: x indicates ?read only? and is a ?don?t care? for th e write mode.res* is a reserved bit and should be ?0? table 11. address pin characteristics v addr add1 add0 v addr -1 ?0001000? 0 0 v addr -2 ?0001001? 0 1 v addr -3 ?0001010? 1 0 v addr -4 ?0001011? 1 1
isl9492 19 fn6547.1 march 17, 2011 layout guidelines it is highly recommended to connect gnd of c1, c6, c14, c2, c15, pins 8 and 9 in a tight form ation on the top layer as shown in red circles in figure 30 and needs to be returned back to the input power supply gnd post, which is on the bottom left of the ISL9492QFNEVAL1 evaluation boar d. the ground side of the components in green circles along with the epad can be dropped to the internal ground plane which connects to the top ground plane with 8-10 vias near c1 to form a star ground connection. refer to an1629 ?isl9492 quick start guide? r4 100 r6 3.3k r1 15 r5 100 c15 0.1f/50v c6 1f/25v c10 0.1f/50v c11 open c12 0.01f/50v c8 0.22f/10v c4 0.047f/50v c5 2200pf/50v d1 b230a l1 10h + c2 100f/ 35v p1 vcc + c1 100f/35v p2 return c14 1f/25v p15 addr_o p16 addr_1 p9 svtop r3 100k p8 td_out scl 1 gnd 2 gnd 3 sda 4 j1 i2c p6 extm p7 txt r2 100k p5 flt l2 220h d2 5smc22a(tvs) p3 lnb c7 0.01f/50v q1 nds356ap cdr7d43mn-100 p11 gnd c13 0.1f/25v power vout lnb_power tdin cpvout sp1 scopeprobe r11 0 r8 0 r9 0 p10 3.3v external vswsns 2 nc 3 nc 4 abyp 5 vcc 6 drain 7 pgnd 8,9 dbypp 10 addro 11 addr1 12 svtop 13 tdin 14 tdout 15 sda 16 scl 17 txt 18 extm 19 ldo_sgnd 20 flt 21 tcap 22 dgate 23 vout 24 ldo_sgnd 25 vsw 26 cpvout 27 cpswout 28 cpswin 1 u1 isl9492 g d s c9 1f/25v l4 mmz2012s102a r12 100 d4 ss25 c16 0.1f l3 1h c3 10f/35v vsw d 3 ss25 r10 100 c18 220nf/50v c17 open top gnd connection drops into middle or bottom gnd plane middle or bottom gnd layer connects to top gnd connection with 6- 10 vias to form a star gnd connection figure 30. isl9492 star ground connection illustration
isl9492 20 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6547.1 march 17, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processi ng functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl9492 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 3/4/11 fn6547.1 changed in typical application schematic on page 1 and page 5 bottom d3 which was duplicated to d4. 3/2/11 added layout guidelines on page 19. 1/28/11 fn6547.0 initial release
isl9492 21 fn6547.1 march 17, 2011 package outline drawing l28.4x4a 28 lead thin quad flat no-lead plastic package rev 1, 12/08 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 4.00 a 4.00 b index area pin 1 6 (4x) 0.15 28x 0.45 0.10 4 28x 0.20 0.10 b 14 8 4x 0.40 24x 2.4 6 pin #1 index area 2 .40 0 . 15 0 . 75 base plane see detail "x" seating plane 0.10 c c 0.08 c 0 . 2 ref c 0 . 05 max. 0 . 00 min. 5 ( 2. 40 ) ( 3. 75 typ ) ( 24x 0 . 4 ) ( 28x 0 . 20 ) ( 28x 0 . 65) 15 22 21 1 28 typical recommended land pattern detail "x" side view top view bottom view a c m

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